Integrated circuit designers often use strobed comparators to achieve extremely high gains and good resolution. A strobed comparator is ideally designed to have low offset, a quick decision time and no static current. A strobed comparator works in two phases, a comparison phase and a reset phase. The comparison phase is carried out by two differentially connected transistors. In the comparison phase, input voltages are supplied to the two differentially connected transistors. A difference in the input voltages results in a difference in current that is fed to a regenerative latch that comprises two cross coupled transistors.
After the comparison phase has been completed, a reset phase is carried out. The regenerative latch must be reset to a balanced state to prepare the regenerative latch for the next comparison phase. The outputs of the strobed comparator become invalid after the strobed comparator has been placed in a reset phase. For this reason, a set reset (SR) latch coupled to the output of the strobed comparator holds the output values during the reset phase.
There are generally three methods to reset a strobed comparator. The first method employs a switch device on the common point of the differential pair of transistors. The second method employs a switch device on the output nodes of the differential pair of transistors. The third method employs a switch device across the regenerative latch in order to short the outputs together or to a common point. The third method is usually employed in conjunction with the first method or the second method in order to ensure a zero static current in the strobed comparator.
For purposes of illustrating the first method, consider an exemplary prior art strobed comparator circuit 100 shown in FIG. 1. The differential pair of transistors comprises N-type metal oxide semiconductor (NMOS) transistors M40 and M41. The regenerative latch comprises P-type metal oxide semiconductor (PMOS) transistors M10, M11, M20 and M21. PMOS transistors M20 and M21 are cross coupled. The switch device on the common point of the differential pair of transistors (M40 and M41) comprises NMOS transistor M31.
A strobe signal (designated “latch_b”) is provided to the gate of NMOS transistor M31. As shown in FIG. 1, the “latch_b” strobe signal is also provided to the gates of PMOS transistors M10 and M11 of the regenerative latch circuit. Prior art strobed comparator 100 provides the lowest value of offset as the differential pair of transistors (M40 and M41) go from the “off” region to the “saturation” region. As a result, the differential pair of transistors (M40 and M41) has a gain that is greater than one (“1”). This gain reduces the effect of the offset from the regenerative latch portion of the circuit.
Furthermore, the strobe signal is common to the differential pair of transistors (M40 and M41) and does not contribute to the offset. The disadvantage of the approach illustrated in strobed comparator 100 is that the input capacitance of the differential pair of transistors (M40 and M41) must be charged by the preceding stage (not shown in FIG. 1) during the comparison phase and discharged during the reset phase. This creates a charge kickback effect in which the outputs of the previous stage create a glitch when the strobed comparator 100 is strobed. This feature makes it very difficult and challenging to design an appropriate preceding stage for strobed comparator 100.
For purposes of illustrating the second method, consider an exemplary prior art strobed comparator circuit 200 shown in FIG. 2. The differential pair of transistors comprises N-type metal oxide semiconductor (NMOS) transistors M40 and M41. The regenerative latch comprises P-type metal oxide semiconductor (PMOS) transistors M10, M11, M20 and M21. PMOS transistors M20 and M21 are cross coupled. The two switch devices on the output nodes of the differential pair of transistors (M40 and M41) comprise NMOS transistors M30 and M31.
A strobe signal (designated “latch_b”) is provided to the gate of NMOS transistor M30 and to the gate of NMOS transistor M31. As shown in FIG. 2, the “latch_b” strobe signal is also provided to the gates of PMOS transistors M10 and M11 of the regenerative latch circuit. Prior art strobed comparator 200 provides a lower value of charge kickback but a much worse value of offset. The differential pair of transistors (M40 and M41) in strobed comparator 200 remains in the “linear” region during the reset phase and continue to be in the “linear” region during the start of the comparison phase. As a result, the differential pair of transistors (M40 and M41) has a gain that is less than one (“1”) and amplifies the offset from the regenerative latch portion of the circuit.
However, because the differential pair of transistors (M40 and M41) remains always in the “on” state, the preceding stage (not shown in FIG. 2) does not have to provide significant charge during the comparison phase and during the reset phase. This reduces the charge kickback effect.
In view of the deficiencies of the prior art, there is a need for a system and method that is capable of providing a strobed comparator circuit that has a reduced value of offset and a reduced level of charge kickback. In particular, there is a need in the art for a system and method that is capable of minimizing the amount of offset and charge kickback in a strobed comparator circuit.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.